1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor device and methods thereof, and more particularly to a semiconductor device including a selectively formed etch stopping layer and methods thereof.
2. Description of the Related Art
As semiconductor devices become more highly integrated, a width and an interval of wires included therein may become narrower. During a formation of a contact hole among parallel wires, an alignment margin of a photolithography process may decrease such that a bad contact or contact failure may be generated. A process for forming a contact hole of a highly integrated semiconductor device may include forming a self-aligned contact hole to improve the alignment margin, as will now be described with respect to FIGS. 1 to 4.
FIGS. 1 to 4 are cross-sectional views illustrating a process of forming a conventional semiconductor device. Referring to FIG. 1, a gate pattern 9 including a gate insulation layer 3, a gate electrode 5 and a capping layer pattern 7 stacked on a semiconductor substrate 1 may be formed. An impurity injection region 13 may be formed in both sides of the gate pattern 9 of the semiconductor substrate 1. Spacers 11 covering both sidewalls of the gate pattern 9 may be formed. An etch stopping layer 15 may be conformably formed on the semiconductor substrate 1. An interval of the gate pattern 9 and a neighboring (e.g., adjacent) gate pattern 9 may be narrowed or reduced by the etch stopping layer 15.
Referring to FIG. 2, an interlayer dielectric layer 17 may be formed on the semiconductor substrate 1 where the etch stopping layer 15 may be formed. As shown, a void V may be formed between adjacent gate patterns 9 (e.g., with an intervening portion narrowed or reduced by the etch stopping layer 15).
Referring to FIG. 3, an upper surface of the interlayer dielectric layer 17 may be planarized to expose an upper surface of the etch stopping layer 15. A mask pattern 19 including an opening exposing a space of the gate patterns 9 may be formed on the interlayer dielectric layer 17. The mask pattern 19 may be used as an etch mask to remove the interlayer dielectric layer 17 between the gate patterns 9 and to form a contact hole 20 exposing the etch stopping layer 15. The exposed etch stopping layer 15 may be etched by the contact hole 20. Because the etch stopping layer 15 may not be easily etched in the relatively narrow portion between the adjacent gate patterns 9, the semiconductor substrate 1 may be not exposed because a portion of the etch stopping layer 15A may remain after the etching process.
In conventional highly integrated semiconductor devices, an interval of adjacent gate patterns 9 may be narrower such that the etch stopping layer 15 covering a sidewall of the spacer 11 between the adjacent gate patterns 9 may reach the etch stopping layer 15 covering a sidewall of another spacer 11 facing the spacer 11. If the remaining portion of the etching stopping layer 15A covers the sidewalls of adjacent spacers, a probability that the remaining portion of the etching stopping layer 15A will block an exposure of the semiconductor substrate 1 may be increased.
Referring to FIG. 4, a conductive material may fill the contact hole 20 to form a contact plug 21. However, as shown in FIG. 4, the contact plug 21 may not contact the impurity injection region 13 because of the remaining portion of the etch stopping layer 15A. Accordingly, a contact failure may be generated because a conductive path may not be achieved between the contact plug 21 and the impurity injection region 13, which may cause semiconductor devices to function improperly.